1. Field of the Invention
The present invention relates to a technique for transferring data between processing units attaining one function or a plurality thereof and in particular to a memory control apparatus and a memory control method utilizing buffer memory effectively in a system LSI comprising a large number of processing units.
2. Description of the Related Art
A conventional system LSI has a configuration of incorporating, on a single chip, plural pieces of functional blocks, which are configured to achieve one function or a plurality thereof. These functional blocks can be regarded as a single processing unit such as a central processing unit (CPU), memory and a dedicated circuit, and a process progresses in the system LSI by exchanging signals or data between the processing units.
As the scale of such a system LSI grows, a problem emerges in exchanging signals between functional blocks, that is, the processing units.
FIG. 1 is a diagram showing the configuration of a system LSI.
Referring to FIG. 1, in the system LSI performing data processing, plural system boards 10 (SB#0), 20 (SB#1) and 30 (SB#2) are interconnected by way of a crossbar switch 40 (XB#0). The system board 30 (SB#2) comprises plural system controllers 31 (SC#0) and 32 (SC#1). Likewise the system board 10 (SB#0) comprises a plurality of system controllers 11 (SC#0) and the like, while the system board 20 (SB#1) comprises a plurality of system controllers 21 (SC#0) and the like.
The system controller 31 (SC#0) controls a read from, and a write to, memory (DIMM) 81, 82, 83 or 84 by way of MAC71 (MAC#00), 72 (MAC#1), 73 (MAC#3) or 74 (MAC#4) in accordance with an instruction from a CPU (not shown in a drawing herein) connected to either of plural CPUs 51 (CPU#0), 52 (CPU#1), and so on, or either of plural system controllers 32 (SC#1), 11 (SC#0), 21 (SC#0), and so on. Further, when reading from, and writing to, the memory (DIMM) 81, 82, 83 or 84, which is controlled by the system controller 31 (SC#0), buffer memory 61 (M0), 62 (M1), 63 (M2) or 64 (M3), which temporarily stores data corresponding to the memory (DIMM) 81, 82, 83 or 84, is utilized.
As the system LSI becomes very large, however, a large number of instructions and/or many pieces of data (i.e., data packets) sometimes converge into the same buffer memory 61 (M0) 62 (M1), 63 (M2) or 64 (M3).
FIG. 2 is a diagram for describing a phenomenon in which many instructions converge into the same buffer memory.
If a plurality of instructions (i.e., requests) from either CPU require data stored in the memory (DIMM) 81, many instructions are converged into the buffer memory 61 (M0), causing it to overflow with instructions, as shown in FIG. 2.
In order to improve such a situation, the capacity of all the buffer memories 62 (M1), 63 (M2) and 64 (M3), not only the buffer memory 61 (M0), must be increased, and there is a resultant cost increase that makes the method impractical, and therefore the present memory 61 (M0) needs to be used more effectively.
There is accordingly a technique (i.e., BUSY control technique) for issuing a BUSY signal inhibiting the transmission of an instruction or the like from a buffer memory 61 (M0) or the like when the buffer memory 61 (M0) or the like no longer has room to receive an instruction and/or data, that is, when the buffer memory 61 (M0) or the like becomes full or nearly full. The BUSY control technique makes it possible to reduce the possibility of the buffer memory 61 (M0) overflowing with instructions and the like.
Another method is to provide each of the CPUs 51 (CPU#0), 52 (CPU#1) and the like, which hand instructions to a single system controller 31 (SC#0), with plural pieces of buffer memory, thereby making it possible to reduce the possibility of causing the buffer memory 61 (M0) to overflow with instructions and the like.
However, although the above described BUSY control technique does not generate a big practical problem when a system LSI is relatively small, the distances between various LSIs, such as the distance between the system boards 10 (SB#0) and 30 (SB#2) and the distance between the system controllers 11 (SC#0) and 32 (SC#1), become longer as the system LSI becomes larger, thus elongating the transmission time between them. As a result, a “slippage” is generated between the instruction and the BUSY signal, causing a problem in which an instruction is issued to a buffer memory 61 (M0) or the like that is actually unable to receive the instruction.
FIG. 3 is a diagram for describing a phenomenon called “slippage” generated between the instruction and a BUSY signal.
Referring to FIG. 3, first, a first instruction issued from the CPU (CPU#0) of the system board 10 (SB#0) in step (1) (shown in the drawing; the numbers in parentheses, through (14), mean the same hereinafter), is handed over to the system controller 31 (SC#0) of the system board 30 (SB#2) by way of the crossbar switch 40 (XB#0) in step (3), under the control of the system controller 11 (SC#0) (in step (2)). This prompts the system controller 31 (SC#0) to access the memory (DIMM) 81 by way of the MAC 71 (MAC#0) (in step (4)).
If the buffer memory 61 (M0) becomes full at this time, one of the BUSY signals inhibiting the transmission of an instruction or the like from the buffer memory 61 (M0) (in step (5)) is handed over to the system controller 11 (SC#0) of the system board 10 (SB#0) by way of the crossbar switch 40 (XB#0) (in step (6)) under the control of the system controller 31 (SC#0) of the system board 30 (SB#2). Then, the BUSY signal is returned to the CPU (CPU#0) of the system board 10 (SB#0), which initially issued the first instruction, under the control of the system controller 11 (SC#0) (in step (7)).
If, however, a second instruction is issued from the CPU (CPU#0) of the system board 10 (SB#0) and if the second instruction is handed over to the system controller 31 (SC#Q) of the system board 30 (SB#2) by way of the crossbar switch 40 (XB#0) (in step (10)) under the control of the system controller 11 (SC#0) (i.e., step (9)), between the transmission of the first instruction (in step (1)) and the receiving of the BUSY signal (in step (7)), then the buffer memory 61 (M0) is already full and the system controller 31 (SC#0) is unable to receive the second instruction. This state is defined as “slippage”.
Note that, even if such a “slippage” occurs, the system controller 31 (SC#0) of the system board 30 (SB#2) returns a response corresponding to the first instruction from the memory (DIMM) 81 by way of the MAC 71 (MAC#0) (in step (11)) and the response is handed over to the system controller 11 (SC#0) of the system board 10 (SB#0) by way of the crossbar switch 40 (XB#0) (in step (13)) under the control of the system controller 31 (SC#0) of the system board 30 (SC#2) (i.e., step (12)). Then, under the control of the system controller 11 (SC#0), the response to the first instruction is returned to the CPU (CPU#0) of the system board 10 (SB#0), which issued the first instruction (in step (14)).
Further, if a configuration is such as to generate a BUSY signal with sufficient time so as to avoid the occurrence of “slippage”, that is, if the configuration is such as to issue a BUSY signal inhibiting the transmission of an instruction or the like from a buffer memory 61 (M0) and the like at the timing when the buffer memory 61 (M0) or the like becomes close to full instead of completely full, a problem is generated in which the capacity of the buffer memory 61 (M0) or the like is partially wasted.
Further, if a configuration is such as to provide all the CPUs with corresponding pieces of buffer memory, the required number of pieces of buffer memory increases with the size of a system LSI, thus giving rise to the problem of cost increase.
FIG. 4 is a diagram for describing the problem in the case of comprising pieces of buffer memory corresponding to all CPUs.
For example, if a single system board comprises four system controllers, with each system controller respectively comprising four CPUs, the number of pieces of buffer memory comprised by each system controller increases from four pieces corresponding to the conventional number of CPUs to sixteen pieces corresponding to sixteen CPUs, that is, between the zeroth and fifteenth. That is, the number of required pieces of buffer memory quadruples from four to sixteen.